1. Field of the Invention
This invention relates to a dual damascene structure, and more particularly, to a dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit, in which low-K (low dielectric constant) dielectric materials are used to form the dielectric layers and the etch-stop layers between the metal interconnects in the integrated circuit.
2. Description of Related Art
A high-density integrated circuit is typically formed with a multi-level interconnect structure with two or more layers of metal interconnects to serve as wiring line structures for the purpose of electrically interconnecting the various components in the integrated circuit. The multi-level interconnect structure typically includes a first layer (base layer) of metal interconnect structure which is electrically connected to the source/drain regions of the MOS transistors in the integrated circuit, and a second layer of metal interconnect structure which is separated from the base metal interconnect structure by an insulating layer, but with the second metal interconnect structure being electrically connected to the base metal interconnect structure via metal plugs formed in the insulating layer. Still another or more metal interconnect structures can be formed over the second layer of metal interconnect structure.
When the integrated circuit is further scaled down to below deep-submicron level of integration, or the metal interconnects are reduced in resistance to raise the access speed to the IC device, the conventional methods to form the metal interconnects would display some drawbacks. For instance, the etching on the low-resistance copper-based metallization layers to form the metal interconnects would be difficult to carry out on a deep-submicron integrated circuit. Moreover, in the deposition process to form di-electric layers between two neighboring levels of metal interconnects, the resulted di-electric layers would be poor in step coverage that may then cause undesired voids or trapping of impurities to occur. One solution to these problems is to form the so-called dual damascene structure, which can help eliminate the above-mentioned drawbacks of the metal interconnect structures formed in deep-submicron integrated circuits by allowing the dielectric layers between the metal interconnects to be highly planarized. A conventional dual damascene structure is illustratively depicted in the following with reference to FIGS. 1A-1F.
Referring first to FIG. 1A, the dual damascene structure is constructed on a semiconductor substrate 100. A base metal interconnect structure 102 is formed in the substrate 100. Next, a first dielectric layer 104 is formed, typically from silicon dioxide, over the entire top surface of the substrate 100, covering the entire exposed surface of the base metal interconnect structure 102. After this, an etch-stop layer 106 is formed, typically from silicon nitride, over the first dielectric layer 104.
Referring next to FIG. 1B, in the subsequent step, a first photoresist layer 108 is formed over the etch-stop layer 106. The photoresist layer 108 is selectively removed to expose a selected portion of the etch-stop layer 106 that is laid directly above the base metal interconnect structure 102 in the substrate 100. Then, with the photoresist layer 108 serving as mask, an anisotropic dry-etching process is performed on the wafer so as to etch away the unmasked portion of the etch-stop layer 106 until the top surface of the first dielectric layer 104 is exposed. As a result, a contact hole 110 is formed in the etch-stop layer 106, which is located directly above the base metal interconnect structure 102 in the substrate 100.
Referring further to FIG. 1C, in the subsequent step, the entire photoresist layer 108 is removed. After this, a second dielectric layer 112 is formed, typically from silicon dioxide, over the entire top surface of the etch-stop layer 106, which also fills up the entire contact hole 110 in the etch-stop layer 106.
Referring further to FIG. 1D, in the subsequent step, a second photoresist layer 114 is formed over the second dielectric layer 112, which is selectively removed to form a trench 116 and a trench 118 therein. The trench 116 is located directly above the contact hole 110 in the etch-stop layer 106 and formed with a greater width than the contact hole 110.
Referring next to FIG. 1E, with the second photoresist layer 114 serving as mask, a second anisotropic dry-etching process is performed on the wafer to a controlled depth until reaching the etch-stop layer 106 and exposing the top surface of the first di-electric layer 104. This forms a trench 116a and a trench 118a in the second dielectric layer 112.
Referring further to FIG. 1F, in the subsequent step, a third anisotropic dry-etching process is performed on the wafer so as to etch away the part of the first dielectric layer 104 that is laid directly beneath the previously formed contact hole 110 (see FIG. 1B) in the etch-stop layer 106 until the top surface of the base metal interconnect structure 102 is exposed. As a result, a contact hole 120 is formed in the first dielectric layer 104, which is connected to the trench 116a in the second dielectric layer 112.
In the subsequent step, a metal is deposited into the contact hole 120 in the first dielectric layer 104 and the trench 116a and the trench 118a in the second dielectric layer 112 to form a dual damascene structure used to electrically connect the base metal interconnect structure 102 to a higher layer of metal interconnect structure (not shown) that is to be formed over the second dielectric layer 112.
In the foregoing dual damascene structure, the dielectric material(s) used to form the first and second dielectric layers 104, 112 and the dielectric material used to form the etch-stop layer 106 should be selected in such a manner as to allow the etching process to act on them with different etching rates. For instance, in the case of the first and second dielectric layers 104, 112 being formed from silicon dioxide, the etch-stop layer 106 is formed from a high-K dielectric material, such as silicon-oxy-nitride or silicon nitride; whereas in the case of the first and second dielectric layers 104, 112 being formed from a low-K dielectric material, such as fluorosilicate oxide, fluorosilicate glass (FSG), hydrogen silsesquioxane (HSQ), or organics, then the etch-stop layer 106 is formed from a high-K dielectric material, such as silicon dioxide, silicon-oxy-nitride, or silicon nitride.
One drawback to the foregoing dual damascene structure, however, is that the dielectric material used to form the etch-stop layer 106 is much greater in terms of di-electric constant than the dielectric material(s) used to form the first and second dielectric layers 104, 112. For instance, the dielectric constant of silicon nitride is about 7.9. Consequently, when electric currents are conducted through the metal interconnects in the dual damascene structure, a large parasite capacitance would occur in the first and second dielectric layers 104, 112 between the metal interconnects. The presence of this parasite capacitance will then cause an increased RC delay to the signals being transmitted through the metal interconnects, thus degrading the performance of the IC device.